Title:
メモリ素子、処理システム、メモリ素子を制御する方法およびダイナミックランダムアクセスメモリを操作する方法
Document Type and Number:
Japanese Patent JP4128234
Kind Code:
B2
Abstract:
The memory device has a circuitry for addressing cells of an array memory of cells in response to at least one address bin. A circuitry exchanges data with an addressed one of the cells. A control circuitry operable to pass an address bit presented at the multiplexed address data input/output to the circuitry for addressing during a first time period. The control circuitry allows for the exchange of data between the circuitry for exchanging and the multiplexed address/data input/ output during a second time period. The first period is defined by a logic high period of a row address strobe received by the memory device and the second period is defined by a logic low period of the row address strobe.
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Inventors:
Gee Earl Mohan Lao
Ronald T. Taylor
Sudher Sharma
Ronald T. Taylor
Sudher Sharma
Application Number:
JP29148395A
Publication Date:
July 30, 2008
Filing Date:
November 09, 1995
Export Citation:
Assignee:
Cirrus Logic,Inc.
International Classes:
G11C8/00; G11C11/401; G11C5/06; G11C11/407; G11C11/41
Domestic Patent References:
| JP6162762A | ||||
| JP6076566A | ||||
| JP4241294A | ||||
| JP6195257A | ||||
| JP4345994A |
Attorney, Agent or Firm:
Hidesaku Yamamoto