HYBRID DATA PROCESSING SYSTEM HAVING BUILT-IN PULS POWER SUPPLY CMOS CIRCUIT

Japanese Patent JPH08251002

A

PROBLEM TO BE SOLVED: To make a communication between different kind of chips by converting a signal of a PPS mode into corresponding binary data of an NRZ CMOS mode corresponding to a binary data signal. SOLUTION: There are many inputs to a PPS-CMOS translating circuit 16. They are a PPS-CMOS data signal generated by a PPS-CMOS circuit on a chip 14, a PPS signal from a PPS oscillation circuit part of a frame 18, and a PPS clock signal from a PPS clock generating circuit part of the frame 18. The circuit 16 converts the PPS data signal into conventional CMOS data corresponding to those signals and the individual signals are applied to a conventional CMOS chip 12 through a lead or a bus 28. Further, the circuit can generate the conventional CMOS clock signal by itself and this clock signal is inputted to a lead 30 when necessary to synchronize a stream of data on the chip 12.

ZADEUSU JIYON GABARA

JP276396A

September 27, 1996

January 11, 1996

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AT & T CORP

H02J3/00; H03K19/0175; H03K19/0185; H03K19/0948; (IPC1-7): H03K19/0175; H02J3/00; H03K19/0948

Masao Okabe (2 outside)

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