To provide a high-quality information processor.
An information processor comprises: a host device 1; a semiconductor memory device 2 having a nonvolatile semiconductor memory 210; and a communication path 3 that connects the host device 1 and semiconductor memory device 2. The host device 1 comprises: a first storage unit 100; and a first control unit 120 to which the first storage unit 100 and communication path 3 are connected, the control unit controlling the first storage unit. The communication path 3 includes a plurality of ports to each of which a priority is assigned. The semiconductor memory device 2 is connected to the communication path 3 and includes a second control unit 200 that transmits, to the first control unit 120, a request including a flag which determines the priority on the basis of a priority order of data transmission/reception operation with the first storage unit 100. The first control unit 120 performs, when receiving the request, transmission and reception of data between the first storage unit 100 and second control unit 200 via a port corresponding to the priority on the basis of the flag that is included in the request.
Yoshihiro Fukuhara
Makoto Nakamura
Nobuhisa Nogawa
Takashi Mine
Naoki Kono
Katsu Sunagawa
Morisezo Iseki
Takao Ako
Tadashi Inoue
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi