PURPOSE: To prevent occurrence of the malfunction in the high-speed operation, by varying the output data of the input control type binary counter circuit with the fall of the clock signal.

CONSTITUTION: Master FF41 contains the serial circuit consisting of MOS transistors Tr56∼58 plus 59∼61 each between the output ends of CMOS inverters 48 and 54 and the earth each. On the other hand, slave FF42 possesses the serial circuit comprising MOSTRs 73 and 74 plus 75 and 76 between the output ends of CMOS inverters 66 and 71 and potential supply end VDD. And the input control type binary counter circuit is formed with FF 41 and 42. Then the output of the counter circuit is varied with the fall of clock signal CK, thus preventing the malfunction which is caused in the high-speed operation.