Title:
INTER-PROCESSOR COMMUNICATION SYSTEM
Document Type and Number:
Japanese Patent JPH01209563
Kind Code:
A
Abstract:
PURPOSE:To avoid the deterioration in data processing efficiency of a 1st processor by performing the transfer of data between a data memory and a 2nd processor while the 1st processor is kept under and access state to a program memory. CONSTITUTION:The data bus and address bus of a data memory 8 are separated from the data and address buses of a processor 1 by an address switching circuit 5 and a data bus switching circuit 9 respectively while the processor 1 is kept under an access state to a program memory 3. Then the output bus of an address counter 6 which produces a prescribed address is connected to the data bus led to another processor 12. Thus the transfer of data is carried out between the memory 8 and the processor 12. As a result, it is not required to stop the working of the processor 1 even in a data transfer mode. Then the deterioration can be avoided for the data processing efficiency.
Inventors:
KIRIHARA MOTONORI
Application Number:
JP3396588A
Publication Date:
August 23, 1989
Filing Date:
February 18, 1988
Export Citation:
Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
G06F15/16; (IPC1-7): G06F15/16
Domestic Patent References:
| JP59096611B | ||||
| JPS61259358A | 1986-11-17 | |||
| JPS5884333A | 1983-05-20 |
Attorney, Agent or Firm:
Toshiaki Suzuki