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Title:
INTERNAL LAYER CONDUCTOR CIRCUIT TREATMENT METHOD
Document Type and Number:
Japanese Patent JP2008258636
Kind Code:
A
Abstract:

To provide an internal layer conductor circuit treatment in which electrical properties are excellent, and variation in wiring and the risk of the generation of failures are suppressed, in a multilayer wiring board, a semiconductor chip mounted substrate, and a semiconductor package substrate.

An internal layer conductor circuit treatment method is such that by immersing a core substrate, in which a conductor circuit pattern 6 is formed, in a polyamidimide solution and drying it, without carrying out surface roughening treatment of the conductor circuit pattern 6 on the core substrate, a polyamidimide adhesion layer 7 with a thickness of 0.1 to 5 m and high moisture absorption thermal resistance is formed as an adhesion promoter on the core substrate.


Inventors:
TAKAI KENJI
MASUDA KATSUYUKI
HASEGAWA KIYOSHI
MORIIKE MICHIO
KAMIYAMA KENICHI
Application Number:
JP2008109192A
Publication Date:
October 23, 2008
Filing Date:
April 18, 2008
Export Citation:
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Assignee:
HITACHI CHEMICAL CO LTD
International Classes:
H05K3/46
Domestic Patent References:
JPH02277297A1990-11-13
JP2003069233A2003-03-07
JP2002137328A2002-05-14
JP2000198855A2000-07-18
Attorney, Agent or Firm:
Hidekazu Miyoshi
Iwa Saki Kokuni
Kawamata Sumio
Masakazu Ito
Shunichi Takahashi
Toshio Takamatsu



 
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