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Patent Searching and Data


Title:
LOOP NETWORK
Document Type and Number:
Japanese Patent JPS6272251
Kind Code:
A
Abstract:

PURPOSE: To eliminate accumulation of jitter on a transmission line by providing a clock generating means unique to each station, a clock extraction means and a means increasing/decreasing the length of a preamble in response to the frequency difference of clocks obtained from both the means in a network of the time division multiplex system.

CONSTITUTION: A reception data is stored in a buffer 15 by a reception clock extracted by a timing extraction circuit 7. A transmission data is outputted from a parallel/serial conversion circuit 27 by a transmission clock generated uniquely from an oscillator 29. A buffer storage quantity detection circuit 31 supervises overflow or underflow of the buffer 15 and sends a signal to a preamble increasing/decreasing device 33 before such a state comes. When the preamble increasing/decreasing device 33 receives the said signal, the device 33 increases/decreases the prescribed number of bits in the 1st 10-bit in a preamble shown in the figure.


Inventors:
KAJI TATSUO
KOKKYO TOMOO
Application Number:
JP21308885A
Publication Date:
April 02, 1987
Filing Date:
September 26, 1985
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H04L7/10; (IPC1-7): H04L7/10; H04L11/00
Attorney, Agent or Firm:
Saichi Suyama