Title:
低電力無線周波数分周器
Document Type and Number:
Japanese Patent JP2012501110
Kind Code:
A
Abstract:
In accordance with the present disclosure, a multi-modulus divider (MMD) circuit configured for operation at high frequencies may include a cascade of multiple divide-by-2-or-3 cells that divides an input clock signal to produce a pulse signal. The MMD circuit may also include a pulse stretching circuit that extends the duration of the pulse signal, thereby outputting an output clock signal. The cascade of divide-by-2-or-3 cells and the pulse stretching circuit may be implemented using full-swing complementary metal-oxide-semiconductor (CMOS) circuits. Each divide-by-2-or-3 cell may be organized so that a critical path of the divide-by-2-or-3 cell comprises a first dynamic flip flop, a second dynamic flip flop, and no more than two logic stages between the first dynamic flip flop and the second dynamic flip flop.
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Inventors:
Ellersick, William Frederick
Application Number:
JP2011524050A
Publication Date:
January 12, 2012
Filing Date:
August 21, 2009
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
H03K23/66; H03L7/08
Other References:
JPN6012034453; Ｓｌｅｉｍａｎ， Ｓ．Ｂ．； Ａｔａｌｌａｈ， Ｊ．Ｇ．； Ｒｏｄｒｉｇｕｅｚ， Ｓ．； Ｒｕｓｕ， Ａ．； Ｉｓｍａｉｌ， Ｍ．: 'Ｗｉｄｅ-ｄｉｖｉｓｉｏｎ-ｒａｎｇｅ ｈｉｇｈ-ｓｐｅｅｄ ｆｕｌｌｙ ｐｒｏｇｒａｍｍａｂｌｅ ｆｒｅｑｕｅｎｃｙ ｄｉｖｉｄｅｒ' Ｃｉｒｃｕｉｔｓ ａｎｄ Ｓｙｓｔｅｍｓ ａｎｄ ＴＡＩＳＡ Ｃｏｎｆｅｒｅｎｃｅ， ２００８． ＮＥＷＣＡＳ-ＴＡＩＳＡ ２００８． ２００８ Ｊｏｉｎｔ ６ｔｈ Ｉｎｔｅｒｎａｔｉｏｎａｌ ＩＥＥ , 2008, Ｐａｇｅｓ １７-２０
Attorney, Agent or Firm:
Kurata Masatoshi
Takakura Shigeo
Satoshi Kono
Makoto Nakamura
Yoshihiro Fukuhara
Takashi Mine
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Morisezo Iseki
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
Takakura Shigeo
Satoshi Kono
Makoto Nakamura
Yoshihiro Fukuhara
Takashi Mine
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Morisezo Iseki
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori