METHOD OF INTEGRATING AND MANUFACTURING Cu GERMANIDE AND Cu SILICIDE AS Cu CAPPING LAYER

Title:

METHOD OF INTEGRATING AND MANUFACTURING Cu GERMANIDE AND Cu SILICIDE AS Cu CAPPING LAYER

Document Type and Number:

Japanese Patent JP2009130369

Kind Code:

A

Abstract:

To provide a method of forming a capping layer on a copper wiring free from damaging surrounding dielectric materials.

This method for forming the capping layer 6 including Cu, N, and Si and/or Ge onto a copper conductive structure 2, includes steps of: forming at least one capping layer onto the copper conductive structure 2 by exposing the structure to a GeH4 and/or SiH4-containing atmosphere 3 at a temperature range from 200 to 400C; performing NH3 plasma processing 5 to form an at least partly nitrided capping layer 6; forming a dielectric barrier layer 7 onto the at least partly nitrided capping layer 6; and pre-annealing the copper conductive structure prior to the step of forming the at least one capping layer in a temperature range from 250 to 450C.

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Inventors:

CHUNG-SHI LIU
CHEN-HUA YU

Application Number:

JP2008299124A

Publication Date:

June 11, 2009

Filing Date:

November 25, 2008

Export Citation:

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Assignee:

IMEC INTER UNI MICRO ELECTR
TAIWAN SEMICONDUCTOR MFG

International Classes:

H01L21/3205; H01L23/52

Domestic Patent References:

JP2006237257A	2006-09-07
JP2000058544A	2000-02-25
JP2007533171A	2007-11-15
JP2000208513A	2000-07-28
JPH11186261A	1999-07-09
JP2004056096A	2004-02-19
JP2006237257A	2006-09-07
JP2000058544A	2000-02-25

Foreign References:

US20070075428A1

2007-04-05

Other References:

JPN6013039946; Ｓ．　Ｃｈｈｕｎ，　外１１名: 'Ｉｍｐａｃｔ　ｏｆ　ｉｎｔｒｏｄｕｃｉｎｇ　ＣｕＳｉＮ　ｓｅｌｆ-ａｌｉｇｎｅｄ　ｂａｒｒｉｅｒｓ　ｉｎ　ａｄｖａｎｃｅｄ　ｃｏｐｐｅｒ　ｉｎｔｅｒｃｏｎｎｅｃｔｓ' Ｍｉｃｒｏｅｌｅｃｔｒｏｎｉｃ　ＥｎｇｉｎｅｅｒｉｎｇＶｏｌ．　８２, 20050818, ｐ．　５８７-５９３
JPN6013039949; Ｓ．　Ｃｈｈｕｎ，　外１７名: 'Ｃｕ　ｓｕｒｆａｃｅ　ｔｒｅａｔｍｅｎｔ　ｉｎｆｌｕｅｎｃｅ　ｏｎ　Ｓｉ　ａｄｓｏｒｐｔｉｏｎ　ｐｒｏｐｅｒｔｉｅｓ　ｏｆ　ＣｕＳｉＮ　ｓｅｌｆ-ａｌｉｇｎｅｄ　ｂａｒｒｉｅｒｓ　ｆｏｒ　ｓｕｂ-６５' Ｍｉｃｒｏｅｌｅｃｔｒｏｎｉｃ　ＥｎｇｉｎｅｅｒｉｎｇＶｏｌ．　８３, 20061017, ｐ．　２０９４-２１００

Attorney, Agent or Firm:

Takuji Yamada
Mitsuo Tanaka
Haruo Nakano

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