Title:
積層電子部品の製造方法
Document Type and Number:
Japanese Patent JP7361250
Kind Code:
B2
Abstract:
A sintered body that includes semiconductor ceramic layers and an internal electrode which are alternately stacked on one another is prepared. A first external electrode is formed on a side surface of the sintered body such that the first external electrode is connected to the internal electrode. An insulating layer is formed on a surface of the sintered body by applying a glass coating over an entire of the sintered body having the formed first external electrode. The insulating layer is exposed from the first external electrode. A second external electrode is formed on the first external electrode. This method provides the produced multilayer electronic component with a stable electric connection between the internal electrodes and the external electrodes.
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Inventors:
Yanai sword
Tomokazu Yamaguchi
Yuji Yamagishi
Naoki Mutoh
Sayaka Matsumoto
Ryosuke Usui
Tomokazu Yamaguchi
Yuji Yamagishi
Naoki Mutoh
Sayaka Matsumoto
Ryosuke Usui
Application Number:
JP2019547963A
Publication Date:
October 16, 2023
Filing Date:
September 19, 2018
Export Citation:
Assignee:
Panasonic IP Management Co., Ltd.
International Classes:
H01C7/10; H01C1/02; H01C7/112; H01C17/00; H01G2/10; H01G4/228
Domestic Patent References:
| JP2000164406A | ||||
| JP8330107A | ||||
| JP2015012052A | ||||
| JP2000223359A | ||||
| JP2000235932A | ||||
| JP6295803A |
Attorney, Agent or Firm:
Kenji Kamada
Kenji Maeda
Kenji Maeda