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Patent Searching and Data


Title:
MEMORY ACCESS CONTROLLING SYSTEM
Document Type and Number:
Japanese Patent JPS6290739
Kind Code:
A
Abstract:

PURPOSE: To make memory access which is suitable for memory access of 4-byte boundary possible even for a computer system which adopts an access system of 8-byte unit, by providing a means which converts the access into 8-byte full store and another means which can make access to every four bytes.

CONSTITUTION: In a computer system provided with partial storing functions, a means which converts access into 8-byte full store if for example, it is detected that the byte mark designation of 8-byte partial store access indicates full store when viewed from the point of 4-byte boundary when the access is made from an CPU or channel processor (CHP), and another means which can make access for every four bytes are installed. Therefore, writing for every four bytes becomes possible and the partial store at the unit of 4-byte boundary becomes a full store process. As a result, the access time is improved and the processing capacity of the said computer system is increased.


Inventors:
TAKAHASHI MASANORI
KURIBAYASHI NOBUHIKO
Application Number:
JP23031685A
Publication Date:
April 25, 1987
Filing Date:
October 16, 1985
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F9/34; G06F12/04; G06F12/06; (IPC1-7): G06F9/34; G06F12/04
Attorney, Agent or Firm:
Sadaichi Igita