Title:
Memory interface structure between chips
Document Type and Number:
Japanese Patent JP6105720
Kind Code:
B2
Abstract:
In an embodiment, a stacked package-on-package system has a memory die and a logic die. The memory die comprises a first memory and a second memory, each operated independently of the other, and each having an inter-chip interface electrically connected to the logic die. The logic die has two independent clock sources, one to provide a first clock signal to the first memory, and the other clock source to provide a second clock signal to the second memory.
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Inventors:
Junwon Soo
Dexter Tee Chun
Dexter Tee Chun
Application Number:
JP2015515261A
Publication Date:
March 29, 2017
Filing Date:
May 31, 2013
Export Citation:
Assignee:
Qualcomm, Inc.
International Classes:
G06F12/00; G06F13/16; G11C5/00; H01L25/10; H01L25/11; H01L25/18; H01L27/10
Domestic Patent References:
| JP2013058277A |
Foreign References:
| US20100325368 |
Attorney, Agent or Firm:
Yasuhiko Murayama
Kuroda Shinpei
Kuroda Shinpei
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