Title:
MEMORY POWER MANAGEMENT USING PREFETCH BUFFER
Document Type and Number:
Japanese Patent JP3935873
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve memory performance and to reduce a power request of a memory.
SOLUTION: A prefetch buffer is added to a memory controller with accompanying prefetch logic. A main memory can stay at a reduced power state until access to the main memory becomes necessary. When the memory controller cannot acquire data for satisfying a memory request from the prefetch buffer, the main memory is switched to an active power state and the prefetch logic is called. The prefetch logic loads requested memory data, returns the requested memory data to the requesting side and loads the memory data possible to be requested in the near future to the prefetch buffer. The memory controller is set at the reduced power state after data acquisition from the main memory.
Inventors:
Hazim Sharphy
Shiva Kumar Belsammy
Shiva Kumar Belsammy
Application Number:
JP2003417332A
Publication Date:
June 27, 2007
Filing Date:
December 15, 2003
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
G06F12/00; G06F1/32; G06F12/08; (IPC1-7): G06F12/00; G06F12/08
Domestic Patent References:
| JP2000148582A | ||||
| JP2002207541A | ||||
| JP10241356A |
Attorney, Agent or Firm:
Hiroshi Sakaguchi
Yoshihiro City
Takeshi Ueno
Yoshihiro City
Takeshi Ueno
Previous Patent: ROTARY SCROLL COMPRESSOR
Next Patent: PATTERNABLE LOW DIELECTRIC CONSTANT MATERIAL AND ITS USE IN ULSI INTERCONNECTION
Next Patent: PATTERNABLE LOW DIELECTRIC CONSTANT MATERIAL AND ITS USE IN ULSI INTERCONNECTION