Title:
METHOD OF INSULATING SILICON DEVICE
Document Type and Number:
Japanese Patent JPS6472529
Kind Code:
A
Abstract:
PURPOSE: To form narrow oxide-filled trenches at a rational rate with a lower cost by forming a narrow rib structures made of a first mask material on a Si base body covered with an etch-stop layer, covering the exposed surface with a resist, removing the rib structures to form trenches in the resist and etching it. CONSTITUTION: The surface of a single crystal Si base body 1 is covered with an etch stop layer 5 and cover layer 7 of a first mask material to form narrow rib structures 17 from the first mask material. The exposed surface is covered with a resist 19, the structures 17 are removed to form trenches into the resist 19, it is etched to form trenches 21 in the substrate 1, and a thermally grown oxide 23 is filled in the trenches 21. After forming an oxide layer 3, polysilicon layer 5 and oxide layer 7 e.g. on the substrate 1, shallow step-like discontinuous parts 11 are formed on the surface of the oxide layer 7, a resist layer thereon is etched by RIE, with leaving thick parts 15 at the roots of the discontinuous parts 11, and using these parts 15 as a mask, the rib structures 17 are formed.
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Inventors:
MAACHIN SEREDEITSUGU ROBAATSU
Application Number:
JP22821387A
Publication Date:
March 17, 1989
Filing Date:
September 11, 1987
Export Citation:
Assignee:
PLESSEY OVERSEAS
International Classes:
H01L21/302; H01L21/3065; H01L21/31; H01L21/76; (IPC1-7): H01L21/302; H01L21/76; H01L21/94
Attorney, Agent or Firm:
Akira Asamura (2 outside)