METHOD OF POLISHING SEMICONDUCTOR SUBSTRATE

Title:

METHOD OF POLISHING SEMICONDUCTOR SUBSTRATE

Document Type and Number:

Japanese Patent JP2006066425

Kind Code:

A

Abstract:

To certainly form a copper interconnection and a copper plug in a chemical mechanical polishing method.

The semiconductor substrate polishing method comprises a first polishing process (step 52) wherein a wafer W is pushed against the polishing surface of a first polishing table, and then the wafer W is polished by relative motion of the polishing surface and the wafer W; and a first water polishing process (step 53) wherein, while injecting a mixed fluid of pure water and gas against the polishing surface of the first polishing table, the wafer W polished in the first polishing process is pushed against the polishing surface of the first polishing table at a bearing pressure of 100 hPa or above, and the object to be polished is polished for 30 seconds or longer by relative motion of the polishing surface and the object to be polished.

Inventors:

KUBO TORU
NOMURA SUEKAZU

Application Number:

JP2004243646A

Publication Date:

March 09, 2006

Filing Date:

August 24, 2004

Export Citation:

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Assignee:

NEC ELECTRONICS CORP
EBARA CORP

International Classes:

H01L21/304; B24B37/00

Domestic Patent References:

JP2002141312A	2002-05-17
JP2002118084A	2002-04-19
JPH0889911A	1996-04-09

Attorney, Agent or Firm:

Akio Miyazaki
Nobuyuki Kaneda
Ishibashi Masayuki

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