Title:
METHOD AND SYSTEM FOR FABRICATING SEMICONDUCTOR
Document Type and Number:
Japanese Patent JP3628825
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To suppress contamination of semiconductor wafer by sustaining a high cleanliness enclosed transferring space of inert atmosphere.
SOLUTION: A semiconductor wafer W is transferred to a reaction chamber 3 while being levitated by ejecting inert gas through nozzles 6 arranged along a transfer passage 2. At the time of processing the semiconductor wafer W in the reaction chamber 3, the semiconductor wafer W is levitated stationarily by ejecting a processing gas, e.g. oxygen gas, through processing gas nozzles 8 and followed by noncontact deposition of an oxide. Subsequently, the inert gas is fed through the nozzles 6 and the semiconductor wafer W is transferred to next process while being levitated.
Inventors:
Yoshio Saito
Masayuki Miyata
Yuhisa Nitta
Masayuki Miyata
Yuhisa Nitta
Application Number:
JP33782696A
Publication Date:
March 16, 2005
Filing Date:
December 18, 1996
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
H01L21/302; B65G49/07; H01L21/3065; H01L21/31; H01L21/324; H01L21/677; H01L21/68; (IPC1-7): H01L21/68; B65G49/07; H01L21/3065; H01L21/31; H01L21/324
Domestic Patent References:
| JP54025166A | ||||
| JP7228342A | ||||
| JP7097049A | ||||
| JP7097050A | ||||
| JP8319564A | ||||
| JP8321497A |
Attorney, Agent or Firm:
Yamato Tsutsui
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