To provide a CMOS multi-input logic gate which can be operated with a small signal amplitude and can reduce power consumption.
The multi-input logic gate has a current source, first and second resistors in which each of one terminal is connected to a power source, m pieces (m is an integer of ≥2) of transistors in which respective sources are connected in parallel to the current source and respective drains are connected in parallel to the other terminal of the first resistor, and m pieces of transistors in which sources and drains are connected in series between the current source and the other terminal of the second resistor. Thus m sets of differential input signals are respectively inputted to the gates of the parallel connected transistors and the gates of the serially connected transistors and outputted from the other terminal of each of the first resistor and the second resistor as differential signals.
| JPH10190446 | DATA ARITHMETIC CIRCUIT |
| JPS54148468 | MULTI-ORDER SWITCHING CIRCUIT |
YAMAGISHI AKIHIRO
TSUKAHARA TSUNEO
NIPPON TELEGRAPH & TELEPHONE