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Title:
MULTILAYER CERAMIC CAPACITOR AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JP2000269074
Kind Code:
A
Abstract:

To prevent delaminations or cracks of the interior of a laminate caused by unbalance of stresses generated during stacking operation in the laminate or by unbalance of sintering properties or shrinkabilities during baking operation, and also to prevent the deformation of the laminate.

This multilayer ceramic capacitor has a laminate 3, having ceramic layers 7 and internal electrodes 5, 6 stacked alternately and also has external electrodes 2 and 2 provided at ends of the laminate 3. The internal electrodes 5 and 6 reach any one of at least one of pairs of opposing edges of the ceramic layers 7, whereby the internal electrodes 5 and 6 are led out to opposing end faces of the laminate 3 and are connected at the end faces of the body 3 to the external electrodes 2 and 2 respectively. Conductor films 8, 8, etc., are formed in a margin zone m, where the internal electrodes 5 and 6 between the ceramic layers 7 are not present.


Inventors:
OTSUKA KOJI
Application Number:
JP7478799A
Publication Date:
September 29, 2000
Filing Date:
March 19, 1999
Export Citation:
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Assignee:
TAIYO YUDEN KK
International Classes:
H01G4/12; H01G4/30; (IPC1-7): H01G4/30; H01G4/12; H01G4/30
Attorney, Agent or Firm:
Kazuyoshi Hojo