To provide an open-loop type clock extraction apparatus for an optical transfer system.
The open-loop type clock extraction apparatus includes: a power divider block for branching an inputted data signal into two signals and outputting them; a first band-pass filter block for extracting a first clock frequency component contained in the data signals outputted from the power divider block; a second band-pass filter block for extracting a second clock frequency component contained in the data signals outputted from the power divider block; a first clock amplification block for amplifying the first clock frequency component extracted from the first band-pass filter block; and a second clock amplification block for amplifying the second clock frequency component extracted from the second band-pass filter block, wherein clock signals corresponding to respective transfer rates can be extracted from data of transfer rates different from each other.
COPYRIGHT: (C)2008,JPO&INPIT
| JPS6447140 | DATA PHASE ADJUSTING CIRCUIT |
| WO/2003/039089 | ZF-BASED ADAPTIVE ASYNCHRONOUS RECEIVER |
| JPH06508969 | [Title of Invention] Clock reproduction |
LEE SANG SOO
LEE HYUN JAE
KO JE SOO
| JPH10150417A | 1998-06-02 | |||
| JP2004088324A | 2004-03-18 |
Kazuo Abe