MULTIPLEXING TRANSMISSION SYSTEM AND APPARATUS

Japanese Patent JP3522247

B2

PROBLEM TO BE SOLVED: To provide a time-division transmission system, having a bandwidth not reduced by a synchronizing signal and a channel identification signal by the use of an interface, having a predetermined frame structure.
SOLUTION: Each channel processing transmitter 1-1-1 to 1-1-n converts an input signal into an internal interface signal. An idle frame inserter 1-2-1 inserts a specific idle frame into the input signal. A multiplexer 1-3 multiplexes each signal on a time-division basis, and a frame portion 1-4 transmits the multiplexed signal to a transmission line 1-5. A frame synchronizer 1-6 performs synchronization on the transmission line 1-5. A channel identifier 1-7 detects a specific idle frame and identifies the multiplexing position of each signal, and a demultiplexer 1-8 demultiplexes each signal, and each idle frame extractor 1-9-1 to 1-9-n eliminates the idle frame. Each of channel processing receivers 1-10-1 to 1-10-n returns each signal to the original interface, to transmit the signal to each of output lines 1-12-1 to 1-12-n.

Shinoda, Hidetoshi

JP2001293929A

April 26, 2004

September 26, 2001

Click for automatic bibliography generation  

NEC CORP

A61L27/00; A61K35/12; A61P1/02; H04J3/00; H04J3/06; H04L7/00; H04L7/04; H04L7/08; (IPC1-7): H04J3/00; H04L7/08

Ａｎｇｅｌａ Ｔ．Ｆａｂｅｒ，ＧＦＰ Ｃｏｎｓｉｄｅｒａｔｉｏｎｓ ｆｏｒ ＲＰＲ，２００１年 ９月，＜ＵＲＬ：ｈｔｔｐ：／／ｗｗｗ．ｉｅｅｅ８０２．ｏｒｇ／１７／ｄｏｃｕｍｅｎｔｓ／ｐｒｅｓｅｎｔａｔｉｏｎｓ／ｓｅｐ２００１／ａｔｆ＿ｇｆｐ＿０２．ｐｄｆ＞
Ｄａｖｉｄ Ｗ．Ｍａｒｔｉｎ，Ｔ１Ｘ１．５／９９−２６８ｒ１ Ｏｖｅｒｖｉｅｗ，ＮＯＲＴＥＬ ＮＥＴＷＯＲＫＳ，２０００年 ３月，＜ＵＲＬ：ｈｔｔｐ：／／ｇｒｏｕｐｅｒ．ｉｅｅｅ．ｏｒｇ／ｇｒｏｕｐｓ／８０２／３／ａｅ／ｐｕｂｌｉｃ／ｍａｒ００／ｍａｒｔｉｎ＿１＿０３００．ｐｄｆ＞
Ｇｅｎｅｒｉｃ Ｆｒａｍｉｎｇ Ｐｒｏｃｅｄｕｒｅ，２００１年，＜ＵＲＬ：ｈｔｔｐ：／／ｗｗｗ．ｉｅｅｅ８０２．ｏｒｇ／１７／ｄｏｃｕｍｅｎｔｓ／ｐｒｅｓｅｎｔａｔｉｏｎｓ／ｍａｙ２００１／ｇｆｐ．ｐｄｆ＞

金田 暢之 （外２名）

Previous Patent: HORSE STARTING MACHINE

Next Patent: SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE