To perform multiplication without generating a large phase difference like the one generated in a PLL circuit.
This multiplication circuit multiplies the input clock signals 150 of a prescribed frequency to the signals 160 of the frequency of (n)-folds (n=2, 3...). A ring oscillator is constituted of a ring oscillator control part 103 and a variable delay circuit 104 and oscillation is stopped when pulses are passed through for (n) times. Also, by matching the oscillation timings of the input clock signals 150 and the (n)-multiplied signals 160 and oscillating the ring oscillator in an almost fixed cycle by a phase comparator circuit 106 and a delay time control part 105, the signals 160 of the frequency of (n)-folds are outputted during one cycle of the input clock signals 150.
| JP2005286804 | SIGNAL GENERATING CIRCUIT |
| WO/1997/040576 | FREQUENCY MULTIPLIER |
MASUDA NOBORU
YAMAMOTO MASAKAZU
