Title:
MULTIPLY CONNECTED NETWORK CHIP PART AND ITS MANUFACTURE
Document Type and Number:
Japanese Patent JPH1174104
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a multiply connected network chip part whose fixing area is small as compared with that of the conventional one. SOLUTION: A plurality of through-holes 11a-11f for connection which penetrate the chip-like substrates 31 -33 are formed through a laminate 5 where a plurality of chip-like substrates 31 , 32 , 33 are stacked and built into an unified body. Electrode portions serving as a plurality of soldering lands are formed on the substrate surface, which is positioned outside the laminating direction of the chip-like substrate 33 positioned at one end of the laminating direction of the laminate 5, corresponding to the through-holes 11a-11f for connection. Conductive paths 12a-12f are formed in the through-holes 11a-11f, respectively and electrically connected to the respective electrode portions. Electrode portions 91a , 91d ,... of electric element members 21 ,... formed on the chip-like substrates 31 -33 are connected electrically to the corresponding electrode portions via the conductive paths 12a-12f.
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Inventors:
AZUMA KOJI
ISHIYAMA ICHIRO
NAGARE ICHIRO
YAMAZAKI MORIKATSU
ISHIYAMA ICHIRO
NAGARE ICHIRO
YAMAZAKI MORIKATSU
Application Number:
JP23402097A
Publication Date:
March 16, 1999
Filing Date:
August 29, 1997
Export Citation:
Assignee:
HOKURIKU ELECT IND
International Classes:
H01C1/14; H01C7/00; H01C13/00; H01C17/06; H05K3/34; (IPC1-7): H01C13/00; H01C1/14; H01C7/00; H01C17/06
Attorney, Agent or Firm:
Hidetoshi Matsumoto (1 outside)
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