Title:
【発明の名称】ドライバ回路
Document Type and Number:
Japanese Patent JP3085130
Kind Code:
B2
Abstract:
A driver circuit comprising (i) a pair of complementary MOS (CMOS) transistors connected in series and receiving an identical input signal, and (ii) a pair of control transistors changing a threshold voltage state of each of the pair of CMOS transistors by applying a plurality of voltages to a body terminal of each of the pair of CMOS transistors depending upon the ON/OFF state of each of the pair of CMOS transistors. Such a driver circuit is capable of reconciling a high-speed operation with a low power consumption under low power supply voltage conditions.
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Inventors:
Susumu Kurosawa
Application Number:
JP6233995A
Publication Date:
September 04, 2000
Filing Date:
March 22, 1995
Export Citation:
Assignee:
NEC
International Classes:
H03K17/567; H01L29/786; H03K17/687; H03K19/00; H03K19/003; H03K19/0175; H03K19/0948; (IPC1-7): H03K17/567; H03K17/687; H03K19/0175; H03K19/0948
Domestic Patent References:
| JP57149A | ||||
| JP817183A | ||||
| JP3123326U |
Attorney, Agent or Firm:
Naoki Kyomoto