Title:
PARALLEL PROCESSOR
Document Type and Number:
Japanese Patent JPS58154060
Kind Code:
A
Abstract:
PURPOSE:To perform the parallel processing with high efficiency, by providing a switching circuit to each processor unit in response to the number of bus bits, and also a bus switch plate to each system bus in response to the number of terminals of each processor, and then controlling these switch circuits and plates by an arbiter. CONSTITUTION:Processor units 1-1-1-n are connected to bus switch circuit parts 4-1-4-n via connectors 3-1-3-n. The system buses N1-N3 connected to a memory part 6 and an arbiter 7 have switch contact that is connected to either one of contacts 5-11-5-3n of the circuits 4-1-4-n. The arbiter 7 controls the make and break of the contact without causing any conflict between the units 1-1-1-n and buses N1-N3. As a result, the increment/decrement and the change of processor units are facilitated, and the parallel processing is possible with high efficiency.
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Inventors:
TAKAGI HARUO
Application Number:
JP3740882A
Publication Date:
September 13, 1983
Filing Date:
March 09, 1982
Export Citation:
Assignee:
OMRON TATEISI ELECTRONICS CO
International Classes:
G06F15/167; G06F13/18; (IPC1-7): G06F15/16
Attorney, Agent or Firm:
Nakamura Shigenobu
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