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Title:
PROGRAMMABLE SWITCHED CAPACITOR CIRCUIT
Document Type and Number:
Japanese Patent JPH03234111
Kind Code:
A
Abstract:

PURPOSE: To decrease an offset voltage by controlling a signal turning on/off a switch connecting to each capacitive element so as to select a capacitive element thereby decreasing a DC transfer gain from an noninverting input of an operational amplifier to an output.

CONSTITUTION: The circuit consists of an operational amplifier A, capacitive elements C-2nO, a 1st switch used to select a capacitor by using selection signals SC1-SCn, a 2nd switch turned on/off by a clock signal of a prescribed frequency and a 3rd switch turned on/off by AND or OR of the clock signal of a prescribed frequency, selection signals SA1-SAn, SB1-SBn. Thus, no switch to select the capacitive elements C-2nC is provided between the switches turned on/off with the clock signal of a prescribed frequency and the effect of a parasitic capacitance by a junction capacitance or the like is not caused thereby decreasing an offset voltage.


Inventors:
OKAMOTO TOSHIYUKI
Application Number:
JP3015890A
Publication Date:
October 18, 1991
Filing Date:
February 08, 1990
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03H19/00; (IPC1-7): H03H19/00
Domestic Patent References:
JPS62117426A1987-05-28
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)