PURPOSE: To generate a pulse which rises at desired time and has desired width without loading hardware.

CONSTITUTION: A counter 4 counts a clock CLK 1 and a counter 6 counts a clock CLK 2 of frequency which is (n) times as high as the CLK 1. They begin to count the clocks according to the command from a synchronizing circuit 5 which synchronizes a trigger signal TRG. Pulse width C is supplied to a register 2 and a comparator 3 outputs logic '1' when the counter 4 counts the CLK 1 by (C-1) cycles. The counter 6 is a ring counter which counts integers 1-(n) cyclically and the counted value at the start of the counting operation is held in a register 7, and a comparator 8 outputs logic '1' each time the counted value of the counter 6 reaches the held value. A flip-flop 10 generates a pulse GEN according to the output of an AND gate 9.