To provide timing pulses with less time delay from clock pulses by inputting the inversion output of a second D type flip-flop to the reset terminal of a first D type flip-flop and taking out signals from the second D type flip- flop.

When delay time in a flip-flop 14 is obtained, it is 3tpd and it becomes 9tpd together with the delay time to an inverter 13. Also, since the flip-flop 15 inputs the output 14Qa of the flip-flop 14 and turns clock signals 2a inputted to a counter 3 to the clock signals, pulses to rise by an N-th clock signal 2a and fall by an (N+1)-th one are obtained from the output 15Q. Thus, an operation waveform 12a is obtained. In this case, when the delay time from the rise of the clock signals 2a at an output terminal 12 is obtained, since the clock signals of the flip-flop 15 are the clock signals 2a inputted to the counter 3, the delay time by the flip-flop 15 becomes only 3tpd.