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Title:
RECEIVING TIMING CONTROLLER
Document Type and Number:
Japanese Patent JP3110084
Kind Code:
B2
Abstract:

PURPOSE: To provide a data communication signal control system capable of automatically corresponding to any connection corresponding to two types of clocks with different phase delays in an ISDN bus connection predicting various connections.
CONSTITUTION: More accurate data output is attained by detecting the delay of a signal slightly changing according to the connection of a bus line and separating it by two different clocks 6 and 7. In short, the clocks 6 and 7 with two different phases are generated, each sampling result is stored in separate buffers 8 and 9, and the right one is selected as the output. Thus, even when the terminal is attached/detached to/from an arbitrary place on the bus line in the ISDN for which many terminals are connected, the data transfer of the terminal as well as the other terminal can be automatically stabilized.


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Inventors:
Kazunori Sakai
Toshinao Suzuki
Application Number:
JP18116291A
Publication Date:
November 20, 2000
Filing Date:
July 22, 1991
Export Citation:
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Assignee:
NEC
Shizuoka NEC Corporation
International Classes:
G06F13/42; H04J3/00; H04J3/06; H04L5/22; H04L7/00; H04L7/08; H04Q5/00; (IPC1-7): H04J3/06; H04L7/00; H04L7/08
Domestic Patent References:
JP633532A
JP63131743A
JP3265323A
JP58202680A
JP62130037A
JP5864849A
JP5869151A
Other References:
ISDN絵とき読本,オーム社(1988−10−1),p.72−73
Attorney, Agent or Firm:
Naotaka Ide



 
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