Title:
REFRESH CONTROL CIRCUIT
Document Type and Number:
Japanese Patent JPH05198170
Kind Code:
A
Abstract:
PURPOSE: To enhance the performance of a device concerned by refreshing a DRAM without interrupting a processing opportunity utilizing a bus of other bus master of a CPU and a DMAC, etc., as much as possible.
CONSTITUTION: Refresh operation is executed (by circuits 5 and 6) during a processing cycle of other bus master while the bus is not used by other bus master. By this method, the use of the bus by other bus master is not interrupted by the refresh operation. Then, in order to execute the refresh without fail even when the processing cycle is not generated over a log period, a circuit 2 for delaying a refresh requesting signal is provided, and even when an output is sent out by this circuit, the refresh is also executed.
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Inventors:
KASHIWAKURA TOSHIHIKO
Application Number:
JP759792A
Publication Date:
August 06, 1993
Filing Date:
January 20, 1992
Export Citation:
Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
G11C11/407; G11C11/406; (IPC1-7): G11C11/406; G11C11/407
Attorney, Agent or Firm:
Nobuyuki Kudo (2 outside)