PURPOSE: To obtain a necessary frequency dividing ratio by reducing the number of bits.

CONSTITUTION: A frequency dividing ratio in each vector read out from a ROM 1 is set up in an accumulated frequency dividing register 2 and its integer part is outputted. A master clock counter 3 counts up master clocks, and when the count value coincides with a signal outputted from the register 2, a comparator 4 generates a sampling clock. Consequently the register 2 accumulates minority parts and the counter 3 returns the count value to '1'.