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Patent Searching and Data


Title:
SEMICONDUCTOR CIRCUIT
Document Type and Number:
Japanese Patent JPS61145929
Kind Code:
A
Abstract:

PURPOSE: To test an internal circuit without increasing the number of terminals by providing an inverter receiving a signal from an internal logic circuit at the input and a clamp circuit clamping the output of the inverter and leading out the inverter output from a signal terminal.

CONSTITUTION: When a signal A of high/low (GND) level is outputted from the 2nd logical circuit 3, the signal is inverted by an inverter 4 and the output is led to a signal terminal 1. A signal B, however, is clamped at a threshold level VF of a diode D, the range of the signal change does not exceed the threshold level of the 1st logical circuit 2. On the other hand, the signal B led out of the signal terminal 1 is checked by monitoring directly the waveform or amplifying the level up to a prescribed switching level by means of an external circuit. Thus, the signal of the internal circuit is tested by using a conventional input terminal.


Inventors:
HAYASHI HIDENORI
SAWAMURA AKIRA
FUJII KIYOUGO
Application Number:
JP26945584A
Publication Date:
July 03, 1986
Filing Date:
December 19, 1984
Export Citation:
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Assignee:
ROHM CO LTD
International Classes:
G01R31/317; H01L21/8238; H01L27/092; G01R31/28; H03K19/0175; (IPC1-7): G01R31/28; H01L27/08; H03K19/00
Attorney, Agent or Firm:
Shigenobu Nakamura