To provide a semiconductor device for controlling an inverter capable of changing and correcting dead time by phase or every PWM period, and a dead time generating method therewith.

A PWM generating circuit 1 is provided with: a PWM duty setting unit 2; a pulse duration modulation circuit 3; a dead time addition circuit 4; an output logic selection circuit 5; a PWM period setting resistor MDPRD; a U phase PWM duty resistor CMPU; a V phase PWM duty resistor CMPV; and a W phase PWM duty resistor CMPW. The pulse duration modulation circuit 3 inputs information from the duty resistors by phase and outputs PWM signals pwm, 0% determination signals and 100% determination signals by phase to the dead time addition circuit 4. In the dead time addition circuit 4, dead time addition in response to duty output values by phase and dead time correction in the case of 0% output and 100% output are performed.