Title:
SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP3821667
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To maintain stability in the contact resistance of a resistive element and transistor characteristics, and at the same time to form the resistive element and a MOS transistor on the same substrate.
SOLUTION: A silicon oxide film 9 is formed on a first insulating polysilicon film 7, and impurities are introduced to the first polysilicon film 7 with the silicon oxide film 6 as a mask for forming a second conductive polysilicon film 11. A third polysilicon film 13 for determining a value of resistance is formed, and a resist pattern 15 is formed (F). The polysilicon films 13 and 11 are subjected to anisotropy etching for forming a resistive element 17 comprising the first polysilicon film 7, second polysilicon films 11 and 11, insulating film 9 for the resistive element, and third polysilicon film 13; and a gate electrode 19 comprising the first and third polysilicon films 11 and 13 (G). After a high-concentration impurity region 23 is formed (H), an interlayer insulating film 25 is deposited for forming a contact hole 27 (I).
Inventors:
Junichi Konishi
Application Number:
JP2001178868A
Publication Date:
September 13, 2006
Filing Date:
June 13, 2001
Export Citation:
Assignee:
株式会社リコー
International Classes:
H01L23/52; H01L27/04; H01L21/3205; H01L21/822; H01L21/8234; H01L21/8244; H01L27/06; H01L27/11; (IPC1-7): H01L21/822; H01L21/3205; H01L21/8234; H01L21/8244; H01L27/04; H01L27/06; H01L27/11
Domestic Patent References:
| JP7147403A | ||||
| JP5055520A | ||||
| JP2000150780A |
Attorney, Agent or Firm:
Shigeo Noguchi