To provide a semiconductor device and a manufacturing method of the same which can reduce chip area.

A semiconductor device according to an embodiment comprises: a laminate which includes a plurality of conductive layers and a plurality of insulation layers each provided every between the conductive layers, and includes a step-like structure part having a step array in which steps of the plurality of conductor layers are arranged in a row in a first direction in a step-wise manner; and a plurality of vias which are provided on respective steps in the step-like structure part and reach the conductive layers of respective steps. The step array includes a deepest part, one step provided adjacently to the deepest part in the first direction and having a level difference of one stage from the deepest part, and a plurality of steps each having a level difference of multiple stages from the respective neighboring steps in the first direction.