To provide a semiconductor device which controls entry to and exit from a power down mode of a semiconductor memory.
This device comprises a plurality of voltage generators for providing operating voltage to the semiconductor memory, a DPD controller for detecting a DPD condition and generating a DPD signal to control the application of the operating voltage to the semiconductor memory, and a circuit for controlling the timing of turning on/off of the voltage generators upon entry/exit of the DPD mode to seduce surge current flowing through the semiconductor memory to less than the maximum current level. Thereby, the entry and exit of DPD can be performed by the minimum current variation. Also, when a DRAM is operated during an entry or exit mode of DPD, an erroneous trigger of a circuit can be prevented.
YOO JAE-HWAN
LEE JONG-EON
JANG HYUN-SOON
