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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS6337270
Kind Code:
A
Abstract:

PURPOSE: To reduce the load in the preparation of test data by a user and to standardize a test, by automatically generating a test signal in an integrated circuit.

CONSTITUTION: A test signal generating circuit 5, a first input buffer 9 and one or more circuit 13 to be tested, a second output buffer 14 and a change-over signal generating circuit 2 for supplying a buffer change-over signal to the first and second buffers 9, 14 are constituted in an integrated circuit. At the time of a test, the test signal generated and outputted from the test signal generating circuit 5 is supplied to the circuit 13 to be tested. Next, the signal taken out from the circuit 13 to be tested is outputted to an external output terminal 17 through the second buffer 14. At the selection time of a user logical circuit, a present test signal is applied to an external input terminal 10 to make it possible to perform the same test regardless of user logic. By this method, the load reduction in the preparation of test data by a user and the stardardization of a test can be performed.


Inventors:
SASAKI TAKESHI
MONMA HIDEO
Application Number:
JP18049086A
Publication Date:
February 17, 1988
Filing Date:
July 31, 1986
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G01R31/3185; G11C29/00; G01R31/28; (IPC1-7): G01R31/28
Attorney, Agent or Firm:
Teiichi Ijiba (2 outside)