Title:
半導体装置およびその試験方法、および半導体集積回路
Document Type and Number:
Japanese Patent JP4036554
Kind Code:
B2
Abstract:
A semiconductor device mounted on a board or the like and having a test circuit, having the function of carrying out a contact test at a low cost on the terminals of the semiconductor, is disclosed. The semiconductor device comprises a terminal test circuit for testing a state of a contact of an external terminal and a test mode control circuit unit. The test mode control circuit unit outputs a signal indicating a first operation mode upon application of a power supply voltage thereto, outputs a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal such as a chip select terminal, and outputs a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes. Preferably, the first operation mode is a terminal test mode, and the second operation mode is a normal operation mode. A method of testing the semiconductor device and a semiconductor integrated circuit, having the test circuit, are also disclosed.
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Inventors:
Yasuo Matsuzaki
Masao Nakano
Toshiya Uchida
Atsushi Hatakeyama
Kenichi Kawasaki
Yasuhiro Fujii
Masao Nakano
Toshiya Uchida
Atsushi Hatakeyama
Kenichi Kawasaki
Yasuhiro Fujii
Application Number:
JP708399A
Publication Date:
January 23, 2008
Filing Date:
January 13, 1999
Export Citation:
Assignee:
富士通株式会社
International Classes:
G01R31/28; G01R31/26; G01R31/3185; G11C29/02; G11C29/56
Domestic Patent References:
| JP6118143A | ||||
| JP5034409A | ||||
| JP2039246A | ||||
| JP9260443A | ||||
| JP5288806A | ||||
| JP4329651A |
Foreign References:
| US6621283 |
Attorney, Agent or Firm:
Takashi Ishida
Shigeru Tsuchiya
Toshio Toda
Masaya Nishiyama
Higuchi Souji
Shigeru Tsuchiya
Toshio Toda
Masaya Nishiyama
Higuchi Souji