Title:
SEMICONDUCTOR IC DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPS60109245
Kind Code:
A
Abstract:
PURPOSE:To enable to make an element structure fine and to improve characteristics by a method wherein the forming regions for an analog element and a digital element are isolated by an oxide film formed by so-called an isoplanar. CONSTITUTION:A thick isolation oxide film 24 formed to reach the bottom of an epitaxial layer 12 from its surface is formed on an isolation diffused layer 16. This oxide film 24 is formed by so-called an isoplanar, and the regions isolating each element forming region are composed of this film 24 and the diffused layer 16. In the forming region for a bi-polar transistor Q1 as the analog element, a p type base diffused layer 38 by selective diffusion of a p type conductivity impurity such as boron and an n<+> type emitter diffused layer 42 and an n<+> type collector diffused layer ON<+> and the like by selective diffusion of a conductivity impurity such as phosphorus with high concentration are formed. On the other hand, in the forming region for the IIL as the digital element, a p type diffused layer forming a base region and an injector region and an n<+> type diffused layer forming a multi-collector region are formed.
Inventors:
KOWASE YASUAKI
INABA TOORU
KUDOU SATOSHI
MURAMATSU AKIRA
INABA TOORU
KUDOU SATOSHI
MURAMATSU AKIRA
Application Number:
JP21616483A
Publication Date:
June 14, 1985
Filing Date:
November 18, 1983
Export Citation:
Assignee:
HITACHI LTD
International Classes:
H01L21/8226; H01L21/331; H01L21/76; H01L21/762; H01L27/082; H01L29/73; H01L29/732; (IPC1-7): H01L27/08; H01L29/72
Attorney, Agent or Firm:
Akio Takahashi