Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS60109244
Kind Code:
A
Abstract:
PURPOSE:To contrive to prevent the generation of a parasitic transistor by a method wherein two lateral transistors are formed in one semiconductor island region electrically isolated from other regions by grooves dug in the surface of a semiconductor substrate, and a groove is dug in the substrate surface between these transistors. CONSTITUTION:A material, where an n<+> type buried layer 2 is buried in the surface of the p<-> type Si substrate 1 by selective diffusion, and where a low concentration n type Si layer 3 is epitaxially grown thereon, is prepared. Next, the grooves 8 and 9 are dug by a dry etching means and the like by the use of a mask of an Si nitride film formed on the surface of the n type Si layer. A mask of an oxide film 11 is formed on the surface of the island region isolated by the grooves, and a p type isolation layer 4 is formed between the bottom of the groove 8 and the substrate. Besides, the ion implantation and diffusion of an impurity B to obtain a p<+> type collector 6 and a p<+> type emitter 5 is performed to the surface of the island region 3a. Thereafter, the titled device is obtained through processes such as n<+> type diffusion for base, contact photoetching, aluminum evaporation, and patterning etching.
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Inventors:
HAIJIMA MIKIO
Application Number:
JP21617983A
Publication Date:
June 14, 1985
Filing Date:
November 18, 1983
Export Citation:
Assignee:
HITACHI LTD
International Classes:
H01L21/8224; H01L21/331; H01L21/76; H01L21/764; H01L27/082; H01L29/73; H01L29/732; (IPC1-7): H01L27/08; H01L29/72
Attorney, Agent or Firm:
Akio Takahashi