To perform high-accuracy A/D conversion while remarkably reducing the number of external terminals to be used for an A/D converter.
During sampling, switches 21-25 are turned on and a switch 26 is turned off. Since a resistor 19 is set to an optimal resistance value during sampling, impedance seen from a node A to the left side is approximately matched with impedance seen from a node B to the left side, and great noise cancel effects can be obtained. During sequential comparison, switches 21-23, 25 are turned off and switches 24, 26 are turned on. Since a resistor 20 is set to an optimal resistance value during sequential comparison, impedance seen from the node A to the left side is approximately matched with impedance seen from the node B to the left side, and great noise cancel effects can also be obtained during sequential comparison.
JPS639230 | DIGITAL ANALOG CONVERTER CIRCUIT |
JPS6112122 | ANALOG-DIGITAL CONVERTER |
JP2000092141 | LEVEL CONTROL CIRCUIT |
JP2007049637A | 2007-02-22 | |||
JP2001036359A | 2001-02-09 | |||
JPH10293999A | 1998-11-04 | |||
JP2005303591A | 2005-10-27 | |||
JP2007049637A | 2007-02-22 | |||
JP2001036359A | 2001-02-09 | |||
JPH10293999A | 1998-11-04 |
US5646622A | 1997-07-08 | |||
US5646622A | 1997-07-08 |
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