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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2005109400
Kind Code:
A
Abstract:

To provide a semiconductor integrated circuit having a device higher in a cutoff frequency fu with respect to noise.

The semiconductor integrated circuit includes a plurality of second conductivity-type deep well layers 9 that are provided on a first conductivity-type semiconductor substrate 8 and are isolated from each other, first conductivity-type back gate well layers 10 each one of which is provided at the second conductivity-type deep well layers 9, second conductivity-type MIS transistor devices 3 each one of which is provided at the first conductivity-type back gate well layers 10 with the first conductivity-type back gate well layers 10 as backgates and are connected in parallel, and second conductivity-type isolated well layers 4 that are provided at the first conductivity-type back gate well layers 10, surround the second conductivity-type MIS transistor devices 3 and reach the second conductivity-type deep well layers 9.


Inventors:
MITSUNAKA TAKESHI
MIYAMOTO MASAYUKI
SUYAMA NAOHIRO
Application Number:
JP2003344381A
Publication Date:
April 21, 2005
Filing Date:
October 02, 2003
Export Citation:
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Assignee:
SHARP KK
International Classes:
H01L21/761; H01L27/08; (IPC1-7): H01L27/08; H01L21/761
Attorney, Agent or Firm:
Hiroshi Yamazaki
Atsushi Maeda