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Patent Searching and Data


Title:
INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH04180249
Kind Code:
A
Abstract:

PURPOSE: To obtain a desired high-voltage IC without damaging the characteristics of a element device to be used in a high-voltage IC, by a method wherein high impurity density buried layer is provided with a structure where the layer does not directly contact with a p-type semiconductor substrate.

CONSTITUTION: Formed is a first n-type epitaxial layer 11 whose resistivity is determined by the withstanding voltage required on a p-type semiconductor substrate 11. Then, an n-type buried layer 2 with a high impurity concentration is formed on a specified position within the epitaxial layer 11, and a second n-type epitaxial layer 3 is formed to bury the n-type buried layer 2. Then, an isolation area 4 is formed which extends to the p-type semiconductor substrate across the first n-type epitaxial layer 11 and the second n-type epitaxial layer 3. Then, a base region 5 and emitter region 6 for a transistor are formed on the island region that is formed by the isolation area 4, and an n-type collector-wall region 7 with a high impurity concentration is formed. Thus, it is possible to obtain a sufficient high withstanding voltage without making the resistivity of the buried layer 2 high.


Inventors:
MITARAI GORO
Application Number:
JP31035890A
Publication Date:
June 26, 1992
Filing Date:
November 14, 1990
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L27/082; H01L21/74; H01L21/76; H01L21/761; H01L21/8222; (IPC1-7): H01L21/74; H01L21/76; H01L27/082
Domestic Patent References:
JPS59124736A1984-07-18
JPS5236483A1977-03-19
Attorney, Agent or Firm:
Kaneo Miyata (3 outside)