Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JPS63122089
Kind Code:
A
Abstract:
PURPOSE: To improve cycle time by inputting an external data in a write circuit via a latch circuit which latches the data in the unit of bit in synchronism with a clock.
CONSTITUTION: If a data held in the data latch circuit 105 insynchronism with a clock input is inputted to the write circuit 106, an output signal is supplied to the bases of respective transistors connected to the digit lines 103 of memory cells 101, to lift/lower the potential of a digit line pair selected by a digit selection circuit 104. With such constitution, stray capacity in the latch circuit can be made small, hence the cycle time can be improved.
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Inventors:
OUCHI MICHIO
Application Number:
JP27015986A
Publication Date:
May 26, 1988
Filing Date:
November 12, 1986
Export Citation:
Assignee:
NEC CORP
International Classes:
G11C11/414; G11C11/34; (IPC1-7): G11C11/34
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)