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Title:
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
Document Type and Number:
Japanese Patent JP2009140966
Kind Code:
A
Abstract:

To provide a semiconductor package which can be downsized and improved in durability against mechanical load, and to provide a manufacturing method thereof.

The semiconductor package 1 is obtained in such a way that a large number of semiconductor chips are mounted on a substrate having a repeatedly formed electrode pattern forming a single unit of semiconductor package and the whole surface of the mounting substrate including a group of the semiconductor chips is sealed with resin and the substrate is divided into individual semiconductor packages, wherein an adhesive layer 5 is formed and interposed between the resin contact surface side of an electrode 31 exposed on a divided end surface and the sealing resin 6. The manufacturing method of the semiconductor package 1 includes: forming the adhesive layer on the resin contact surface of the electrode pattern exposed on the divided end surface after the semiconductor chip 4 is mounted on the substrate 2, sealing the whole surface of the substrate mounting surface including the group of the semiconductor chips with resin, and dividing the substrate into individual semiconductor packages after the sealing resin 6 is cured.


Inventors:
OUCHI TSUTOMU
KIMURA KIMIHIKO
Application Number:
JP2007312653A
Publication Date:
June 25, 2009
Filing Date:
December 03, 2007
Export Citation:
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Assignee:
ARS DENSHI KK
International Classes:
H01L23/29; H01L21/56; H01L23/12; H01L23/28; H01L23/31
Domestic Patent References:
JP2002016193A2002-01-18
JP2005019935A2005-01-20
JP2002151805A2002-05-24
Attorney, Agent or Firm:
Hirofumi Mizuno