To avoid reduction of a forward current caused by microfabrication.

A semiconductor storage element of an embodiment comprises a cell array layer including first wiring, memory cells laminated on the first wiring and second wiring formed on the memory cells. The memory cell includes a current control element, a variable resistive element and a metal layer for a silicide that is arranged between the current control element and the variable resistive element. A semiconductor storage element manufacturing method comprises: forming first wiring or a first wiring layer; sequentially forming, on the first wiring or the first wiring layer, a semiconductor layer in which the current control element is formed, the metal layer for the silicide and a variable resistive element layer in which the variable resistive element is formed; selectively removing the variable resistive element layer and the metal layer for the silicide until reaching the semiconductor layer by first etching; forming a first protection layer so as to cover at least an exposed lateral face of the metal layer for the silicide; selectively removing a part of the semiconductor layer corresponding to a selectively removed part by second etching; and forming a second protection layer so as to cover the variable resistive element, the metal layer for the silicide and the semiconductor layer.