Title:
SEMICONDUCTOR STORAGE
Document Type and Number:
Japanese Patent JP3877104
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To set optional external potential even for bit line pre-charge potential together with cell plate potential by providing a switch circuit conducting plural storage cell potential connected to a bit line through a transistor and the bit lines with pre-charge potential.
SOLUTION: Plural storage cells are connected to the bit line through the transistor. An internal potential generation circuit 81 is constituted of the transistor 82, switches 11-15 and resistors 83-88. The switch 24 is made open, and the switch 25 is made closed, and an internal voltage vii is supplied, and further, the switches 1, 4 are made open, and the switch 3 is made closed. The transistors 38, 41 go to the on-state, and cell plate potential vcp is connected to bit line pre-charge potential vpr. The internal voltage (1/2)vii is cut off from the bit line pre-charge potential vpr. At this time, an optional external voltage is applied from an external pad.
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Inventors:
Kazuo Hayashi
Kazufumi Kazuyuki
Kazufumi Kazuyuki
Application Number:
JP20561498A
Publication Date:
February 07, 2007
Filing Date:
July 21, 1998
Export Citation:
Assignee:
富士通株式会社
International Classes:
G01R31/28; G11C29/06; G11C11/401; G11C11/409; G11C29/00; (IPC1-7): G11C29/00; G01R31/28; G11C11/409; G11C11/401
Domestic Patent References:
| JP1273292A | ||||
| JP4230047A |
Attorney, Agent or Firm:
Tadahiko Ito