To provide a semiconductor wafer, which its provided with a reference pattern for preventing an erroneous recognition and is formed with a recongnition mark for ensuring the reliability of the alignment of the wafer.

A plurality of semiconductor elements 32, which are respectively formed with an integrated circuit, are provided on a semiconductor wafer 30, a plurality of scribing lines, which are formed of horizontal and vertical scribing lines 36 and 34 which section these elements 32 and separate the elements 32 on the wafer 30 into individual semiconductor chips, are provided on the wafer 30 and a recongnition mark 40 is provided at the intersecting point where the lines 36 intersect the lines 34 so that the wafer 30 is aligned at a prescribed position to cut the wafer 30. Moreover, a dark region, which is formed of a plurality of horizontal and vertical lines, and a bright region encircling this dark region are provided on the mark 40.