Title:
SEMICONDUCTOR WAFER PROCESS CHAMBER HAVING SUSCEPTOR BACK COATING
Document Type and Number:
Japanese Patent JP3699147
Kind Code:
B2
Abstract:
PURPOSE: To eliminate unsuitable temperature display and the dilution of deposited gas by providing a material layer deposited on a wafer for the back surface facing a surface supporting the wafer in a susceptor for a device depositing the material layer on the wafer.
CONSTITUTION: In a semiconductor wafer processor 10, hydrogen purge gas is flowed into a line feeding deposited gas into a base introduction port. Thus, deposited gas sent to the base introduction port flows into the upper part 22 of a deposition chamber 12 and it crosses the central part of the susceptor 20. The deposited gas is diluted by hydrogen gas much more than deposited gas crossing the outer part of the wafer and entering the deposition chamber 12. Deposited gas passing through the outer part of the wafer is diluted by hydrogen crossing the end part of the susceptor 20 from the lower part 24 of the deposition chamber 12 and flowing upward. Thus, the material of deposited gas leaked into the lower part 24 of the deposition chamber 12 is deposited on the rear face of the susceptor 20.
Inventors:
Roger N. Anderson
H. Peter W. Hay
Israel baingrass
Mahallingham vencatesan
H. Peter W. Hay
Israel baingrass
Mahallingham vencatesan
Application Number:
JP7686495A
Publication Date:
September 28, 2005
Filing Date:
March 31, 1995
Export Citation:
Assignee:
APPLIED MATERIALS,INCORPORATED
International Classes:
C30B25/08; C23C14/50; C23C16/455; C23C16/458; C30B25/10; C30B25/14; H01L21/205; H01L21/31; C23C16/44; (IPC1-7): H01L21/205; C23C14/50; H01L21/31
Domestic Patent References:
| JP5102041A | ||||
| JP4233723A |
Attorney, Agent or Firm:
Yoshiki Hasegawa
Tatsuya Shioda
Shiro Terasaki
Yuichi Yamada
Tatsuya Shioda
Shiro Terasaki
Yuichi Yamada