シャロートレンチアイソレーションプロセス - Taiwan Semiconductor Manufacturing Company,Ltd.

Title:

シャロートレンチアイソレーションプロセス

Document Type and Number:

Japanese Patent JP4585510

Kind Code:

B2

Abstract:

A structure including a transistor and a trench structure, with the trench structure inducing only a portion of the strain in a channel region of the transistor.

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Inventors:

Curie, matthew, tee
Rock Tefeld, Anthony, Jay

Application Number:

JP2006509191A

Publication Date:

November 24, 2010

Filing Date:

March 05, 2004

Export Citation:

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Assignee:

Taiwan Semiconductor Manufacturing Company,Ltd.

International Classes:

H01L21/76; H01L21/00; H01L21/26; H01L21/336; H01L21/42; H01L21/762; H01L21/8234; H01L21/8238; H01L27/00; H01L27/08; H01L27/088; H01L29/00; H01L29/06; H01L29/10; H01L29/772; H01L29/78; H01L29/786; H01L31/0328; H01L31/0336; H01L31/072; H01L31/109; H01L

Domestic Patent References:

JP2001244468A
JP2002270834A
JP2001284599A

Attorney, Agent or Firm:

Satoshi Furuya
Takahiko Mizobe
Kiyoharu Nishiyama

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