Title:
SIMULATION DEVICE AND METHOD THEREFOR
Document Type and Number:
Japanese Patent JP3731922
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To easily and quickly perform the logical simulation or the timing simulation of the whole of an analog/digital coexisting LSI.
SOLUTION: Because a simulation means regards an analog macro cell as a digital macro cell performs a timing simulation based on pseudo input/output timing data and the whole timing simulation can be performed in also an analog/digital coexisting LSI. Because the simulation means regards the analog macro cell as the digital macro cell and performs the simulation based on pseudo digital data, the logical simulation of the whole of the analog/digital coexisting LSI can be performed. Thus, the handling time for the development of the analog/digital coexisting LSI can be reduced and the mistake at the time of the development can be reduced.
Inventors:
Hideaki Kida
Koichi Otsuki
Koichi Otsuki
Application Number:
JP17517195A
Publication Date:
January 05, 2006
Filing Date:
July 11, 1995
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F17/50; (IPC1-7): G06F17/50
Domestic Patent References:
| JP4074272A | ||||
| JP8030662A | ||||
| JP8160103A |
Attorney, Agent or Firm:
Yasuo Ishikawa
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